For thinning the wafers before certain process steps, such as for example sawing or loading with components, the substrates are ground on the back side. A method of doing this that is known from practical use is one in which the front sides of the wafers are laminated with a protective film. The wafer is fixed with the laminated front side on the vacuum grinding table (vacuum chuck) and thinned by means of diamond-impregnated grinding wheels while cooling water is additionally applied.
The protective film is also intended to equalize and even out process-dependent differences in height in the circuits on the wafer. Pronounced topographies in the semiconductor circuit or pronounced substrate thinnings cause local nonuniform variations in the thickness of the substrate (dimples) during the grinding. Resultant mechanical stresses in the substrate can lead to cracks and chip rupture. In particular, in the case of more recent forms of flip-chip mounting, metal connectors (bumps) with a height of up to 150 μm are additionally applied on the front side, serving for direct contacting on printed circuit boards. These high bumps can no longer be smoothly covered with conventional protective films. Back-side thinning below a substrate thickness of 300 μm without any deterioration is problematic.
Topographies on the wafer with a height of up to 50 μm can be equalized by means of thicker layers of adhesive on the protective films. However, possible remains of adhesive, and consequently increased contamination, pose a risk to the reliability of component mounting operations. Evening out by means of additional layers of lacquer on the surface of the wafer, and in particular their removal/disposal, make the process considerably more expensive. For even higher contact bumps, special films are being developed; the price of such films is twice that of the existing standard material.
The “protective film lamination” and “protective film removal” processes require dedicated devices of their own. In the laminating device, the protective film is adhesively attached to the upper side of the wafer and cut-off flush at the periphery of the wafer by a heated knife running around it. Thinning of the back side by grinding is followed in the peeling device by fixing the wafer on a vacuum chuck, adhesively attaching a special peeling adhesive tape and peeling off the protective film from the wafer while supplying ionized air (to counteract electrostatic charging during the peeling off of the film). These method steps are laborious.
Previously, the grinding thin of the wafers had to be performed before applying the contact bumps, which involved increased risk of rupture of the thin wafers in the subsequent metallizing and etching processes.
Various methods and devices that are concerned with the problems of fixing wafers on assembly carriers are also known from the patent literature. Some of these address the difficulties of fixing wafers on assembly carriers when the wafers are to be thinned.
One example of such a literature reference is European Patent publication, EP 1 148 554 A1, U.S. counterpart U.S. Pat. No. 6,683,332 B2. Described there is a method for the highly accurate and rapid thinning of a semiconductor substrate, which can be performed independently of the tolerance of an assembly carrier and an adhesive join with which the substrate is attached to the assembly carrier. For this purpose, a first doped layer with p dopant is formed in the substrate. Subsequently, the substrate is initially ground down from its back side and further etched back wet-chemically. In this case, the first doped layer serves as an etching resist. In this document, the following literature reference is cited by way of example as prior art: “Semiconductor Wafer Bonding: Science and Technology, Q. Y. Tong, Wiley-Interscience Publication”. There it is described on pages 1 to 13 that, in the case of such a method, the process of thinning the semiconductor substrate is one of the technologically most demanding and expensive process steps. For the three-dimensional integration, usually two ready-processed wafers are first provided. The first wafer serves in this case as a carrier, the second wafer is thinned by the following method and arranged on the first wafer. For thinning, the second wafer is first provided with a layer of adhesive on its front side, which is the side with the electric circuits, and is then connected to an assembly carrier. The second wafer is then thinned from its back side, usually up to three methods being used sequentially.
The first method to be used is usually a grinding method, which is followed by a chemical etching method and chemical-mechanical polishing (CMP). The aim of this method is to retain a residual thickness of the semiconductor substrate in the range of 10 μm, special importance having to be attached to the planarity and the exact maintenance of the target thickness. On account of the different ways in which they work, the three thinning methods mentioned each entail different disadvantages, so that the best result is achieved by a combination of the known methods. Grinding is the quickest method, and is therefore used as the first step, in order to remove the greatest part of the semiconductor layer.
However, grinding causes deteriorations of the substrate surface, which are removed in a subsequent chemical etching step. The chemical etching step has the disadvantage, however, that the etched surface is not planar but has a waviness in the range of ±3%, the layer thickness removed by the etching step. For this reason, chemical-mechanical polishing CMP is carried out in a third step, whereby the waviness of the surface is polished out. The CMP step is slow and expensive and is therefore only used for the post-treatment of the surface. The mechanical grinding is used as the method with the greatest removal. The adjustment of the installation means that the removal during grinding occurs plane-parallel to the assembly carrier to which the second substrate wafer is attached.
Here it must be taken into consideration that a wafer that is not attached plane-parallel to the assembly carrier is ground away obliquely. Since the substrate wafer is attached to the assembly carrier, for example, by adhesive, there is an adhesive join between the substrate and the assembly carrier. If the adhesive join has a different layer thickness, as formed for example in the case of a wedge shape, the substrate is not aligned plane-parallel to the assembly carrier. In the subsequent grinding process, the substrate wafer is therefore not ground away plane-parallel to the surface in which the electric circuits are arranged. This problem can be solved, for example, by the adhesive join being made very thin. However, this has the disadvantage that no filled adhesives can be used, adhesives which would be advantageous during the later detachment of the substrate from the assembly carrier, since, for example, solvent can remove the adhesive more easily from thick adhesive joins. Likewise, the adjusting accuracy of the assembly carrier with respect to the grinding plate is transferred into the accuracy of the grinding process. On the other hand, it is not possible to dispense with the grinding process, since etching processes are too inaccurate and CMP is too slow.
There is, for example, a known method in which a buried oxide layer is used as an etching resist. Wafers which have such a buried oxide layer are known as SOI (silicon on insulator) wafers. These wafers are much more expensive than standard wafers and require a modified process procedure in the production of circuits in the silicon substrate as compared with conventional silicon wafers. This necessitates an adaptation of the process technology. Particularly disadvantageous in the case of SOI wafers is that they have great internal mechanical stresses. If SOI wafers are thinned to a few 10 μm and below, this leads to the silicon layer peeling off from the assembly carrier and to the silicon layer rolling up.
Devices that work differently are also known. For example, European Patent publication, EP 0 737 546 B1, U.S. counterpart U.S. Pat. No. 5,791,973, specifies as prior art a device which serves for the chemical-mechanical polishing of semiconductor substrates. As already mentioned, chemical-mechanical polishing is also referred to by the abbreviation CMP, which will be used hereafter.
In the cited documents, a description is given of a device which has a turntable that comprises a planar surface and consists of stable material, so that it is of a sufficiently rigid configuration. By means of the driven rotary shaft, the turntable is turned in a predeterminable direction. On the surface of the turntable there is a polishing pad and/or a polishing material. Above the turntable there is a holding head for the substrate to be polished, for example, a semiconductor wafer, referred to hereafter as wafer for short. The substrate holding head may likewise be formed in a rotatable manner. With the aid of the substrate holding head, the substrate to be polished is pressed against the polishing pad and polished on account of the relative rotational movements under the action of the abrasive material. The polishing operation takes place under certain contact pressure, and it may happen that the substrate to be polished becomes detached from the substrate holding head and moves over the turntable in an uncontrolled manner. This can cause damage to the device. If this happens, the substrate in any case becomes unusable.